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M62334P/FP, M62339P/FP
8-bit 4ch I2C BUS D/A Converter with Buffer Amplifiers
REJ03D0866-0300 Rev.3.00 Jun 15, 2007
Description
The M62334/M62339 is an integrated circuit semiconductor of CMOS structure with 4 channels of built in D/A converters with output buffer operational amplifiers. The input is 2-wires serial method is used for the transfer format of digital data to allow connection with a microcomputer with minimum wiring. The output buffer operational amplifier employs AB class output circuit with sync and source drive capacity of 1.0 mA or more, and it operates in the whole voltage range from VCC to ground. The M62334 and the M62339 differ only in their slave address.
Features
* Digital data transfer format: I2C BUS serial data method * Output buffer operational amplifier It operates in the whole range from VCC to ground. * High output current drive capacity: 1.0 mA over
Application
Conversion from digital data to analog control data for home-use and industrial equipment. Signal gain control or automatic adjustment of display-monitor or CTV.
Block Diagram
VCC 8 SCL 7 SDA 6 GND 5
Power on reset
I2C BUS transceiver
Channel decoder 8
8-bit latch
8-bit latch
8-bit latch
8-bit latch
8-bit upper segment R-2R
8-bit upper segment R-2R
8-bit upper segment R-2R
8-bit upper segment R-2R
+-
+-
+-
+-
1 AO1
2 AO2
3 AO3
4 AO4
REJ03D0866-0300 Rev.3.00 Jun 15, 2007 Page 1 of 9
M62334P/FP, M62339P/FP
Pin Arrangement
M62334P/FP M62339P/FP
AO1 AO2 AO3 AO4 1 2 3 4 8 7 6 5 VCC SCL SDA GND
(Top view) Outline: PRDP0008AA-A (8P4) [P] PRSP0008DE-C [FP] (recommend) PRSP0008DA-A (8P2S-A) [FP] (not recommend for new design)
Pin Description
Pin No. 6 7 1 2 3 4 8 5 Pin Name SDA SCL AO1 AO2 AO3 AO4 VCC GND Power supply terminal GND terminal Function Serial data input terminal Serial clock input terminal 8-bit resolution D/A converter output terminal
REJ03D0866-0300 Rev.3.00 Jun 15, 2007 Page 2 of 9
M62334P/FP, M62339P/FP
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature VCC Vin VO Pd Topr Tstg Symbol Ratings -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 417 (P) / 272 (FP) -20 to +85 -55 to +125 Unit V V V mW C C
Electrical Characteristics
(VCC = +5 V 10%, GND = 0 V, Ta = -20 to +85C unless otherwise noted)
Limits Item Supply voltage Supply current Symbol VCC ICC Min 2.7 0 0 Input leak current Input low voltage Input high voltage Buffer amplifier output voltage range Buffer amplifier output drive range Differential nonlinearity Nonlinearity Zero code error Full scale error Output capacitate load Buffer amplifier output impedance IILK VIL VIH VAO IAO SDL SL SZERO SFULL CO RO -10 0 0.8 VCC 0.1 0.2 -1.0 -1.0 -1.5 -2.0 -2.0 -- -- Typ 5.0 1.4 0.9 -- -- -- -- -- -- -- -- -- -- -- 5.0 Max 5.5 3.0 2.0 10 0.2 VCC VCC VCC - 0.1 VCC - 0.2 1.0 1.0 1.5 2.0 2.0 0.1 -- Unit V mA mA A V V V V mA LSB LSB LSB LSB F CLK = 500 kHz operation, IAO = 0 A Data: 6Ah (at maximum current) SDA = SCL = GND, IAO = 0 A VIN = 0 to VCC Test Conditions
IAO = 100 A IAO = 500 A Upper side saturation voltage = 0.3 V Lower side saturation voltage = 0.2 V VCC = 5.12 V (20 mV/LSB) without load (IAO = 0)
REJ03D0866-0300 Rev.3.00 Jun 15, 2007 Page 3 of 9
M62334P/FP, M62339P/FP
I2C BUS Line Characteristics
Item SCL clock frequency Time the bus must be free before a new transmission can start Hold time START condition (After this period, the first clock pulse is generated) Low period of the clock High period of the clock Set-up time for START condition (Only relevant for a repeated START condition) Hold time DATA Set-up time DATA Rise time of both SDA and SCL lines Fall time of both SDA and SCL lines Set-up time for STOP condition Note: Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Min. 0 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.0 Max. 100 -- -- -- -- -- -- -- 1000 300 -- Unit kHz s s s s s s ns ns ns s
Transmitter must internally provide at least a hold time to bridge the undefined region (300 ns Max) of the falling edge of SCL.
Timing Chart
tR, tF tBUF
VIH SDA VIL
tHD:STA
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
VIH SCL VIL tLOW tHIGH
Start
Start
Stop
Start
REJ03D0866-0300 Rev.3.00 Jun 15, 2007 Page 4 of 9
M62334P/FP, M62339P/FP
I2C BUS Format
STA Note: Slave address W A Sub address A DAC data A STP STA: start condition, A: affirmation bit, W: write (SDA = Low), STP: stop condition
* Slave address
M62334
First 1 0 0 1 1 0 Last 0
M62339
First 1 0 0 1 1 1 Last 1
* Sub address
First X X X X X X S1 Last S0
Channel select data S1 S0 0 0 1 1 0 1 0 1
Channel Selection
ch1 selection ch2 selection ch3 selection ch4 selection
Don't care
Channel select data
* DAC data
First MSB D7 First MSB D7 0 0 0 0 : 1 1 D6 0 0 0 0 : 1 1 D5 0 0 0 0 : 1 1 D4 0 0 0 0 : 1 1 D3 0 0 0 0 : 1 1 D2 0 0 0 0 : 1 1 D1 0 0 1 1 : 1 1 D6 D5 D4 D3 D2 D1 D0 Last LSB D0 0 1 0 1 : 0 1 DAC output VCC / 256 x 1 VCC / 256 x 2 VCC / 256 x 3 VCC / 256 x 4 : VCC / 256 x 255 VCC Last LSB
REJ03D0866-0300 Rev.3.00 Jun 15, 2007 Page 5 of 9
M62334P/FP, M62339P/FP
Timing Chart (Model)

SDA
1
2
3
4
5
6
7
W
A
SCL
D/A output
Start condition _{SDA 1 2 3 4 5 6 7 8 A
SCL
D/A output

SDA 1 2 3 4 5 6 7 8 A
SCL
D/A output
Stop condition
* Start condition With SCL at High, SDA line goes from High to Low * Stop condition With SCL at High, SDA line goes from Low to High (Under normal circumstance, SDA is changed when SCL is Low) * Acknowledge bit The receiving IC has to pull down SDA line whenever receive slave data. (The transmitting IC releases the SDA line just then transmit 8-bit data.)
Digital Data Formats
STA Slave address W A Sub address 1 A DAC data 1 A
............
Sub address 2
A
DAC data 2
A
Sub address n
A
DAC data n
A
STP
REJ03D0866-0300 Rev.3.00 Jun 15, 2007 Page 6 of 9
M62334P/FP, M62339P/FP
Precaution For use
* Supply voltage terminal (VCC) is also used for D/A converter upper reference voltage setting. If ripple or spike is input this terminal, accuracy of D/A conversion is down. So, when use this device, please connect capacitor among VCC to GND for stable D/A conversion. * This IC's output amplifier has an advantage to capacitive load. So it's no problem at device action when connect capacitor (0.1 F Max) among output to GND for every noise eliminate. * Purchase of Renesas's I2C components conveys a license under the Philips I2C Patent Rights to use these components an I2C system, provided that the system conforms to I2C Standard Specification as defined by Philips.
Application Example
1 AO1 2 AO2 5V 3 AO3 4 AO4 SCL 7 SDA 6 GND 5 MCU VCC 8 + 10 F
5V
Analog output terminals
REJ03D0866-0300 Rev.3.00 Jun 15, 2007 Page 7 of 9
M62334P/FP, M62339P/FP
Package Dimensions
JEITA Package Code P-DIP8-6.3x8.84-2.54 RENESAS Code PRDP0008AA-A Previous Code 8P4 MASS[Typ.] 0.5g
8
5
c
1
4
*1
e1
E
*2 D
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
A
Reference Symbol
A2
Dimension in Millimeters
SEATING PLANE *3 b 3 bp e *3 b 2
e1 D E A A1 A2 bp b2 b3 c e L
Min Nom Max 7.32 7.62 7.92 8.7 8.9 9.1 6.15 6.3 6.45 4.5 0.51 3.3 0.4 0.5 0.6 0.9 1.0 1.3 1.4 1.5 1.8 0.22 0.27 0.34 15 0 2.29 2.54 2.79 3.0
JEITA Package Code P-SOP8-4.4x4.85-1.27
L
RENESAS Code PRSP0008DE-C
Previous Code --
A1
MASS[Typ.] 0.1g
*1
D
F
8
5
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE E
*2
Index mark
Terminal cross section ( Ni/Pd/Au plating )
1 Z e 4
*3
c
Reference Symbol
Dimension in Millimeters
bp
x
M L1
A1
L
y
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
A
A2
Min Nom Max 4.65 4.85 5.05 4.2 4.4 4.6 1.85 0.00 0.1 0.20 2.03 0.34 0.4 0.46 0.15 0.20 0.25 0 8 5.7 6.2 6.5 1.12 1.27 1.42 0.12 0.10 0.75 0.25 0.45 0.65 0.90
REJ03D0866-0300 Rev.3.00 Jun 15, 2007 Page 8 of 9
M62334P/FP, M62339P/FP
JEITA Package Code P-SOP8-4.4x5-1.27 RENESAS Code PRSP0008DA-A Previous Code 8P2S-A MASS[Typ.] 0.07g
8
5
HE
*1
E
F
1
Index mark
4
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
c
A2 A1
*2
D
Reference Symbol
Dimension in Millimeters
*3 e y
bp
D E A2 A1 A bp c HE e y L
Detail F
Min Nom Max 4.8 5.0 5.2 4.2 4.4 4.6 1.5 0.05 1.9 0.35 0.4 0.5 0.13 0.15 0.2 0 10 5.9 6.2 6.5 1.12 1.27 1.42 0.1 0.2 0.4 0.6
A
REJ03D0866-0300 Rev.3.00 Jun 15, 2007 Page 9 of 9
L
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